Fine-grained fault-tolerant adaptive routing for networks-on-chip
Liu, J, Harkin, J, Maguire, L, Li, Y, Wan, L and Luo, Y 2015, 'Fine-grained fault-tolerant adaptive routing for networks-on-chip' , in: Algorithms and Architectures for Parallel Processing : 15th International Conference, ICA3PP 2015, Zhangjiajie, China, November 18-20, 2015, Proceedings, Part IV , Lecture Notes in Computer Science (9531) , Springer International Publishing, pp. 492-505.
Restricted to Repository staff only
Download (804kB) | Request a copy
Due to the increase of physical defects in advanced manufacturing processes, Networks-on-Chip (NoC) system reliability is a critical challenge as faults often occur post manufacturing. Therefore it is important to add fault tolerance to the NoC system. In this paper, a novel routing algorithm for 2D mesh NoCs is proposed which aims to enhance the fault-tolerant capabilities via a look-ahead function. A traffic status informing mechanism is developed to provide information to local NoC routers on the interconnect conditions in far distant routers. In addition, a weighted path mechanism is used to forward the packets. The routing algorithm is implemented and verified on FPGA hardware. Real-time throughput and traffic information were collected by a monitoring unit on the FPGA. Results show that the proposed routing algorithm can maintain the system function under low fault rates and only has a marginal (~5 %) throughput degradation under high fault rate of 20 %. The router area is also relatively low which demonstrated its scalability.
|Item Type:||Book Section|
|Schools:||Schools > School of Computing, Science and Engineering|
|Publisher:||Springer International Publishing|
|Series Name:||Lecture Notes in Computer Science|
|Funders:||Non funded research|
|Depositing User:||Yuhua Li|
|Date Deposited:||06 Jan 2016 09:42|
|Last Modified:||06 Jan 2016 09:42|
Actions (login required)
|Edit record (repository staff only)|