High-speed railway timetable rescheduling method : a bi-level integrated programming approach

Zhang, H, Jia, LM, Wang, Li, Qin, Y and An, M ORCID: https://orcid.org/0000-0002-1069-7492 2018, High-speed railway timetable rescheduling method : a bi-level integrated programming approach , in: 3rd International Conference on Electrical and Information Technologies for Rail Transportation (EITRT) 2017, Oct 20, 2017 - Oct 22, 2017, Changsha, China.

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Abstract

China’s railway has experienced a large-scale development in the recent years. Making up for delay time considering the energy efficiency when the train is delayed, which can satisfy the travel demand for passengers and save rail energy costs at the same time, will become the focus of future research on the railway. A bi-level programming optimization model is proposed in this paper. In the upper layer, the high-speed railway timetable is adjusted under unexpected interferences, and then the energy saving is optimized in the lower layer. A real-world case study is presented to illustrate the validity of the model and algorithm.

Item Type:	Conference or Workshop Item (Paper)
Schools:	Schools > School of the Built Environment > Centre for Urban Processes, Resilient Infrastructures & Sustainable Environments
Journal or Publication Title:	Proceedings of the 3rd International Conference on Electrical and Information Technologies for Rail Transportation (EITRT) 2017
Publisher:	Springer
Series Name:	Lecture Notes in Electrical Engineering
ISBN:	9789811079887; 9789811079894
ISSN:	1876-1100
Related URLs:	Publication
Funders:	National Key Research and Development Programme of China, Beijing Jiaotong University State Key Laboratory of Rail Traffic and Control 225 and Safety
Depositing User:	Professor Min An
Date Deposited:	29 Mar 2019 15:29
Last Modified:	29 Nov 2019 12:37
URI:	http://usir.salford.ac.uk/id/eprint/50809

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